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systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.19 $ version: rev 4 clocks sdctl vl clocks sequoia tv sequoia clocks sequoia clocks isa ser1t ser2t ir sequoia sdctl cpu cpu romcard sequoia tv sequoia clocks vl sheet 3, video controller, vga and lcd outputs video sdram sheet 2, sdram and address and data buffers cpu sdctl clocks sequoia vbat sequoia.rcrst sequoia.pbat sequoia.pwrgood clocks clocks clocks sheet 6, sequoia core logic, boot rom and ide interface isa sequoia vl sequoia clocks clocks isa audio sheet 10, audio (mike in, headphone out) and gameport clocks sheet 5, clock generation and rom card interface romcard sequoia clocks vl pciumi sheet 7, pci bridge, umi1 and umi0 vl sequoia clocks isa ser1shdn sequoia ir ser2t ser1t sheet 9, rs232 interface and ir interface serial clocks clocks vbat ser1shdn superio sheet 8, super i/o, keyboard/mouse and parallel ports ser1t ser2t ir sequoia isa clocks isa sheet 12, power supply and backup battery makes p5000*, p3300* and p2000* rcrst vbat pbat power pwrgood sheet 11, ethernet sequoia vl ether isa vl sequoia sheets 13 to 16 show the bypass capacitors and are included as required by the other sheets clocks sequoia tvout sheet 4, tv output encoder and filter tv sequoia clocks ser1shdn isa sdctl clocks romcard vl cpu sequoia cpupal sheet 1, cpu, pal and 3.3v to 5v buffers isa nc reference design
systems research center palo alto, ca title: by: $date: 1997/05/16 23:22:15 $ mark hayter rcs $revision: 1.36 $ version: rev 4 cpu/pal 1 of 16 [0..7] [8..15] [16..23] [24..31] vl.data ~sysden sysddir ~sysden sysddir cpu.d[0..7] cpu.d[8..15] cpu.d[16..23] cpu.d[24..31] ~sysaen ~sysaen cpu.a[2..9] cpu.a[10..17] cpu.a[18..21] cpu.~be [2..9] [10..17] [18..21] vl.adr vl.~be cpu.a[30] cpu.a[29] .~be .d .a nc* ~rw ~mreq cpu nwait nwait .maa .mab .muxsel .~rasa .~rasb .~casa .~casb .~web .~wea .~cs rh rh rh rh rh rh .~ads .~brdy .~rdy .~blast .~local[0] .adr[31] .adr[27] sysddir ~sysden dbe dbe [2..4] [10..12] .a ~sysaen .~rdoeba .rdoeab sdctl vl romcard.wp .hold .hlda vl lvc04 1 2 34 56 98 11 10 13 12 vl.hlda abe vl.sreset ~res note: lvc04 is ok with 5v inputs ~res ~fiq ~irq ~irq sequoia.intr ~fiq gnd* gnd* gnd* gnd* gnd* gnd* gnd* gnd* gnd* gnd* gnd* nc* gnd* p3300* p3300* p3300* nc* abe c0 c1 c2 c3 rh rh rh rh c0 c1 c2 c3 selectively populate res high or low to set core speed bootmd high on reset abe abe note: dir is high for a->b nc* ~rw sequoia.smi rh p5000* note: expected use is smi causes fiq pc[4] configured as gpcs3 used to clocks.cpumclk nc* abt abt gnd* p3300* clocks.nmclk clocks.vlcopy fiq i2:1k i3:1k i4:1k i7:1k i8:1k i9:1k i10:1k i6:1k i5:1k i11:1k i15:33r i16:33r i17:33r i18:33r i19:33r i20:33r u0: u1: u2: u3: u4: u5: u6: u7: ua ub gnd* gnd* note: if the pulldowns on nwait and dbe are removed the cpu input pads will be driven past maximum vih i22:1k p5000* gnd* p5000* act00 11 8 6 3 13 12 10 9 5 4 2 1 rh clocks.clk14m 14.31818mhz i23:33r p5000* clocks.forcpu cclk cclk keep cclk path short or add terminator romcard.~oe romcard.~cs vl.wnr i21:1k r6x33 [23..31] 2 1 43 osc out vcc oe gnd nc* nc* nc* rhr rhi rhi rhi rhi rhi rhi p3300* p5000* b1: b2: note:2 pairs used sheet 2 note: 2 pairs used sheet 6 .~reset romcard.~we .dnc .mnio tp tp2: t1 tp tp8: bypass pwr 10 pairs of 0.1uf and 0.001uf (sheet 16) bypass pwr 10 pairs of 0.1uf and 0.001uf (sheet 16) tp tp23: tp tp24: [2..5] tp25: tp26: [0..3] [6..9] tp27: tp cpu.a[27] tp9: rhi .~brdy rhi p5000* .~rdy i12:4k7 i13:4k7 .adr[25] t tp4 [4] [] t tp4 [4] [] t tp4 [4] [] rh clocks.clk14mb i24:33r f0 f2 f1 m0 m1 m2 m3 m4 m5 [26] cpu.a[26] cpu.a[24] cpu.a[23] cpu.a[22] [24] [23] [22] nc* cpu.a[27] 71 65 72 121 70 69 138 139 57 68 67 66 56 140 142 130 131 50 52 49 48 51 [] [0..31] [] [0..3] [] [2..31] 144 143 141 127 36 122 61 60 62 58 59 124 123 128 sa110 clk mclk nmclk seq mreq rw clf lock abort dbe wait reset fiq irq adr be data tms tdo tdi tck trst testclk tck_byp sna pwrslp mse mccfg0 mccfg1 mccfg2 config cccfg0 cccfg1 cccfg2 cccfg3 ape abe spdf resetout 24 1 25 48 3v3 or 5v [] [8] [] [8] [] [8] [] [8] 3v3 5v 74fct164245 ft164245 b1 b2 a1 a2 oe1 oe2 dir1 dir2 24 1 25 48 3v3 or 5v [] [8] [] [8] [] [8] [] [8] 3v3 5v 74fct164245 ft164245 b1 b2 a1 a2 oe1 oe2 dir1 dir2 24 1 25 48 3v3 or 5v [] [8] [] [8] [] [8] [] [8] 3v3 5v 74fct164245 ft164245 b1 b2 a1 a2 oe1 oe2 dir1 dir2 24 1 25 48 3v3 or 5v 26 27 29 30 [] [4] 37 38 40 41 [] [4] 23 22 20 19 [] [4] 12 11 9 8 [] [4] 3v3 5v 74fct164245 f164245h b1 b14 b15 b16 b17 b2l b24 b25 b26 b27 a1 a14 a15 a16 a17 a2l a24 a25 a26 a27 oe1 oe2 dir1 dir2 sdctl.bootmd .adr[23] .adr[22] tp tp11: tp tp3: uc isa.~refresh r8x33 flashwp refresh ba22 ba23 hlda reset hold clk486 romcardwe romcardoe romcardcs vlmnio vldnc ba25 ba27 ba31 memldev blast rdy brdy ads test2 test1 bootmd sysddir sysden sysaen ahi amid alow rw mreq mclk cpudbe rdoeba rdoeab cs web wea casb casa rasb rasa muxsel malob maloa wait sharkpal mach231-6 3v3 world 24 [0..2] [] [0..2] [] 38 28 27 68 66 7 6 [0..7] [] 70 40 72 65 26 4 [2..4] [] [10..12] [] [23..31] [] either 16 15 17 25 82 52 5v world 9 50 45 49 8 48 46 51 39 69 19 10 18 81 33 13 67 30 23 83 35 clear fiq p5000* vl.~loc0or1 vl.~local[1] vl.~local[0] lor vl.~boff rhi p5000* i25:1k
systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.23 $ version: rev 4 2 of 16 [0..15] [0..15] [0..15] [0..15] [16..31] [16..31] [16..31] [16..31] [0..15] [16..31] cpu.d[0..15] sdctl.~rdoeba sdctl.~web sdctl.~casb sdctl.~rasb sdctl.~cs[4] sdctl.~cs[6] sdctl.~wea sdctl.~casa sdctl.~rasa sdctl.~cs[0] sdctl.~cs[2] [3] [4] [5] [6] [7] [8] [9] sdctl.maa sdctl.mab sdctl.muxsel sdctl.muxsel cpu.a[13] cpu.a[14] cpu.a[15] cpu.a[16] cpu.a[18] cpu.a[19] cpu.a[17] cpu.a [5] [6] [7] [8] [9] [22] [23] note: muxsel is high for ras, low for cas sdctl.muxsel cpu.~be[0] cpu.~be[1] cpu.~be[2] cpu.~be[3] cpu.~be[0] cpu.~be[1] cpu.~be[2] cpu.~be[3] clocks.nmclk dramdata [21] lata21 lata21 lata21 note: this latch shuts when the mux swings to cas address sdram sequoia.sda p3300* sequoia.scl p3300* gnd* sequoia.sda sequoia.scl gnd* lata22 lata22 lata22 lata23 lata22 lata23 lata22 lata23 note: sda/scl is i2c made in software through sequoia and open collector (5v world) buffers gnd* u1: u2: u3: gnd* gnd* u4: u5: u6: i3:1k i4:1k i5:1k gnd* u7: madr clocks.sdrama clocks.sdramb gnd* clocks.dbus clocks.dbus gnd* cpu.d[16..31] gnd* u8: clocks.dbus clocks.dbus gnd* sdctl.rdoeab rh i7:10k rh i8:10k gnd* rh i9:10k rh i10:10k gnd* sdctl.rdoeab i11:10k i12:10k gnd* i13:10k gnd* i14:10k rh i15:33r rh i16:33r rh i17:33r rh i18:33r rh i19:33r rh i20:33r rh i21:33r rh i22:33r rh i23:33r rh i24:33r rh i25:33r rh i26:33r rh i27:33r rh i28:33r rh i29:33r rh i30:33r ma10ap cpu.a[20] rhr rhr rhr rhr rhr rhr note: gets two pairs of bypass caps from sheet 1 p3300* bypass5 pwr 5 pairs of 0.1uf and 0.001uf (sheet 15) i31:10k rhr i32:10k rhr i33:10k rhr i34:10k rhr i35:10k rhr i36:10k rhr i37:10k rhr i38:10k rhr p3300* note: bootmd is high (outputs disabled) on reset lata9 lata8 lata7 lata6 lata5 p3300* m3 m4 m5 m6 m7 m8 m9 m10 b0 b1 b2 b3 b4 b5 b6 b7 sdbeb[3] sdbea[3] sdbeb[2] sdbea[2] sdbeb[1] sdbea[1] sdbeb[0] sdbea[0] sdbeb [0] [1] [0] [1] [2] [3] [2] [3] sdbea [0] [1] [0] [1] [2] [3] [2] [3] note: the slightly perverse assignment of the 32 data bits to the 64 sdram bits results from the way cs0 and cs2 are connected on the module g0 g1 g2 g3 g4 g5 g6 g7 rh tiehi tiehi tiehi tiehi 11 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 3v3 part 74fct3573 fct3573i o0 o1 o2 o3 o4 o5 o6 o7 oe d0 d1 d2 d3 d4 d5 d6 d7 le 1 13 14 10 11 6 5 3 2 15 12 9 7 4 3v3 part 74lvc257 lvc257 za zb zc zd oe a0 a1 b0 b1 c0 c1 d0 d1 s 1 13 14 10 11 6 5 3 2 15 12 9 7 4 3v3 part 74lvc257 lvc257 za zb zc zd oe a0 a1 b0 b1 c0 c1 d0 d1 s 63 128 115 111 [] [0..3] 39 122 129 45 114 30 27 132 126 123 38 [] [3..9] [] [0..2] 167 166 165 83 82 131 130 113 112 47 46 29 28 [] [16] [] [16] [] [16] [] [16] sddimm dll dlh dhl dhh dqmb0 dqmb1 dqmb2 dqmb3 dqmb4 dqmb5 dqmb6 dqmb7 sda scl sa0 sa1 sa2 malo mami ma10ap ma11 ma12 ma13 we s0 s1 s2 s3 ba0 ba1 ck cas ras cke0 cke1 63 128 115 111 [] [0..3] 39 122 129 45 114 30 27 132 126 123 38 [] [3..9] [] [0..2] 167 166 165 83 82 131 130 113 112 47 46 29 28 [] [16] [] [16] [] [16] [] [16] sddimm dll dlh dhl dhh dqmb0 dqmb1 dqmb2 dqmb3 dqmb4 dqmb5 dqmb6 dqmb7 sda scl sa0 sa1 sa2 malo mami ma10ap ma11 ma12 ma13 we s0 s1 s2 s3 ba0 ba1 ck cas ras cke0 cke1 11 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 3v3 part 74fct3574 fct3574i o0 o1 o2 o3 o4 o5 o6 o7 oe d0 d1 d2 d3 d4 d5 d6 d7 cp clkab leab oeab clkba leba oeba a17 a16 a b17 b16 b ft163501 74fct163501 3v3 part [16] [] 33 31 [16] [] 24 26 27 28 30 1 2 55 clkab leab oeab clkba leba oeba a17 a16 a b17 b16 b ft163501 74fct163501 3v3 part [16] [] 33 31 [16] [] 24 26 27 28 30 1 2 55 sdctl.bootmd sdctl.~cs[1] sdctl.~cs[3] sdctl.~cs[5] sdctl.~cs[7]
systems research center palo alto, ca title: by: $date: 1997/05/12 06:22:39 $ mark hayter rcs $revision: 1.27 $ video adra adra adra datab dataa dataa datab nc* nc* nc* nc* nc* casal casah oeab casbl casbh adra adra datab dataa casal casah casbl casbh .~ads .mnio .wnr .~rdy .~local[1] .~be .adr[2..27] .data cv cv fb fb fb cv cv fb fb cv cv gnd* pvideo* cv cv gnd* note: for these power pins care must be taken with layout. c&t 65550 data book section a.10 page a-4 [0] = high vl-bus [2] = high 1x clock [5] = low extclk 14.3mhz [5] [6] = low a26,a27 [6] [7] = high test disable [8] = low ivcc = 3.3v adra [10] = low edo [11] = panel id0 [12] = panel id1 [13] = panel id2 [14] = panel id3 [15] = sw defined dataa [2] [3] [4] [5] [6] [7] rh p5000* nc* nc* nc* nc* [0..7] [8..15] adrc[0..7] link enavdd enavdd note: the lcd section is for experimentation. the rfi filters suggested by c&t are not fitted the signals are simply brought out to a connector note: this connector has the same pinout as the c&t development kit connector nc* might want fuse to +5v on vga pwr adrc version: rev 4 3 of 16 vl .~reset u1: u2: u3: u4: i1:1k i2:33r i3:33r i4:33r i5:33r i6:33r i7:33r i8:33r i9:33r i10:33r i11:33r i12:33r i13:33r i14:33r u5: pvideo* i15:10r i16:0.1uf i17:47uf i18:0.1uf i19:0.1uf i20:47uf i21:0.1uf i22:10r avcc i22:1000pf i23:1000pf i24:560r i25a:37r5 i26a:37r5 i27a:37r5 i28:4.7uh i29:22uf i30:0.1uf i31:0.047uf gnd* i32:4k7 i33:4k7 i34:4k7 i35:4k7 i36:4k7 i37:4k7 i38:4k7 i39:4k7 gnd* i40: i41: i42: i43: i44: i46: i48: i50: cv cv cv i53:220pf i51:220pf 11 12 4 15 5 10 8 7 6 3 2 1 14 13 9 vgacon pwr hsync vsync red green blue redrtn grnrtn bluertn syncrtn grnd id3 id2 id1 id0 gnd* gnd* gnd* hsout vsout rout gout bout rasab0a rasab0b weaa weab rasab1a rasab1b weba webb plcd shfclk flm lp m cvcc0 cvcc1 enavee .vlbus2 .clk32k .clk14m clocks i52:220pf induct cva5 cva6 cva6 lcdpwr 1 2 3 5 8 7 10 11 13 [] [0..7] [] [8..15] [] [8] lcdcon ptop pmid plow shfclk flm lp m de enabkl veesafe v12000safe vddsafe dbav99 dbav99 dbav99 rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhr rhi rhi rhi rhi rhi rhi rhi rhi p5000* (sheet 16) 10 pairs of 0.1uf and 0.001uf pwr bypass rh i54:100k tp .~local[1] tp10: note: care must be taken with placing these caps note: i24, the 560r res on rset must be 1% or better i25, i26 and i27 pulldowns must be 2% or better tried using sequoia.pc[3] for standby, but chip must be out of standby during reset or it does not configure p5000* [] [0..8] [] [0..15] 27 13 28 29 14 dram512kx8 mt16c257 ras casl cash we oe data adr [] [0..8] [] [0..15] 27 13 28 29 14 dram512kx8 mt16c257 ras casl cash we oe data adr [] [0..8] [] [0..15] 27 13 28 29 14 dram512kx8 mt16c257 ras casl cash we oe data adr [] [0..8] [] [0..15] 27 13 28 29 14 dram512kx8 mt16c257 ras casl cash we oe data adr c0 c1 m0 m1 m2 m3 m4 m5 m6 m7 m8 rs bo go ro tv.b rvi i25b:37r5 tv.g rvi i26b:37r5 tv.r rvi i27b:37r5 gnd* note: if no tv out is needed a and b can be replaced with a 75r for each of i25-27 rv rv rv de tv.h tv.v enbk eeok v12ok vddok 181 80 108 142 158 66 42 9 59 56 [] [0..15] [] [0..15] 100 102 103 104 101 [] [0..8] 124 123 125 126 155 157 159 160 156 [] [0..8] 99 178 203 154 27 [] [0..31] [] [2..27] [] [0..3] 25 24 23 11 31 22 207 55 57 58 60 64 65 208 206 202 205 61 62 69 68 67 70 [] [0..15] (vl-bus) chips F65550B ct65550 p shfclk flm lp m enavdd enavee cvcc0 cgnd0 cvcc1 cgnd1 hsync vsync red green blue rset reset ads mnio wnr rdyrtn lrdy ldev be adr data lclk c32khz xtal1 stndby href aa rasab0 casal casah wea oeab0 casbl casbh rasab1 web ca rasc cascl casch wec oec mad mbd agnd avcc bvcc0 bvcc1 dvcc mvcca mvccb mvccc ivcc0 ivcc1 pvideo* p5000* bus, memory and digital i/o 5v power i55:4k7 rhi [8] link p5000* p3300* for the latest revision 65550 c&t recomend that the core only be run at 3.3v. this is a change from earlier revs, there is at least one problem (probably timing) so rev 4 has a link to allow both voltages note: remove i55 for 5v operation pwr: cv i58:0.001uf cv i57:0.1uf cv i56:0.1uf gnd*
systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.10 $ version: rev 4 4 of 16 tv out p5000* p5000* f*4 ntsc clocks.clk14m p5000* gnd* cva4 c4:10uf cv c5:0.1uf p5000* gnd* cva4 c7:10uf cv c6:0.1uf cha8 rh r1:75r c1:220uf fb i1: cha8 rh r2:75r c2:220uf fb i2: cha8 rh r3:75r c3:220uf fb i3: rca 3 4 21 din4 compout ch ch ch c10:0.1uf c9:0.1uf c8:0.1uf .r .g .b .h .v tv sequoia.pc[3] vr vg vb vo vy vc or yr cr oc yc cc yout cout dgnd dpos fin stnd select encd vsync hsync bin gin rin agnd apos crma luma cmps ad724 10 11 9 4 2 6 7 8 16 15 5 12 1 3 14 13
systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.26 $ version: rev 4 clocks 5 of 16 romcard.~oe romcard.~oe romcard.~cs romcard.~cs vl.data[16..23] vl.data[24..31] vl.data[8..15] vl.data[0..7] [0..7] [16..23] [24..31] [8..15] romdata romadr romcard.~cs romcard.~oe romcard.wp [2..5] [6..9] [10..13] [14..17] gnd* [2..5] [6..9] [10..13] [14..17] vl.adr gnd* [18..25] romcard.~we sequoia.smart[3] sequoia.sda u1: u2: u3: u4: [18..25] cv p3300* gnd* p3300* p3300* p3300* gnd* gnd* ck33 rh clocks.sequref clocks.vlcopy rh clocks.cpumclk nc* nc* rh rh rh rh rh rh rh rh clocks.sdrama[0] clocks.sdrama[1] clocks.sdrama[2] clocks.sdrama[3] clocks.sdramb[0] clocks.sdramb[1] clocks.sdramb[2] clocks.sdramb[3] rh rh clocks.nmclk clocks.dbus p5000* nc* clocks.clk14mb rh clocks.clk3m clk7m clocks.forcpu u5: u6: i1:10uf i2:0.1uf i3:0.1uf i4:24r i5:24r i6:24r i7:24r i8:24r i9:24r i10:24r i11:24r i12:36r i13:30r i14:56r i15:51r i16:47r xtal ch i18:1m clocks.clk32k i19:15pf i20:32.768khz gnd* gnd* gnd* nc* nc* nc* gnd* note: these are the isa clock divided by 4, ie 3.5795mhz ish sequoia.pbat p5000* p5000* p5000* gnd 7 14 vcc 1 2 34 56 98 11 10 13 12 c4069 clocks.clk33m gnd* p5000* u7:33.333mhz cvr 2 1 43 osc out vcc oe gnd cva4 note: clock ordering set for rev.4 layout cv i21:0.1uf cv i22:0.1uf cv i23:0.1uf cv i24:0.1uf gnd* p3300* recomended bypass caps: one per digital vcc p5000* note: 7 bypass pairs this sheet, 3 for sheet 7. bypass pwr 10 pairs of 0.1uf and 0.001uf (sheet 16) note: think about rom data bus when roms not active does it need tie offs, or for the pal to keep it active? rhi p5000* i25:10k vl.~reset rh i26:47r ~romwe c1 c2 cx c3 cb cc q5 q4 q3 q2 q1 q0 lf 5 11 7 6 4 18 12 10 9 8 25 2 28 23 21 16 14 26 19 3v3 part 74fct388915t f388915t lock qq q0 q1 q2 q3 q4 q5 qd2 vccan lf gndan freqsel pllen oenrst refsel sync0 sync1 feedback 11 12 10 13 8 9 3 2 4 1 6 5 74act74 act74 q0 qb0 r0 s0 d0 cp0 q1 qb1 r1 s1 d1 cp1 rhi oe4 oe3 oe2 oe1 a4 a3 a2 a1 y4 y3 y2 y1 fct16244 74fct16244 5v part [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] 1 48 25 24 oe2 oe1 a9 a8 a y9 y8 y fct827 74fct827 5v part [8] [] 15 14 [8] [] 10 11 1 13 rh i17:33r c33 rh i27:51r ckfb dir2 dir1 a2 a1 oe2 oe1 b2 b1 fct16245 74fct16245 5v part [8] [] [8] [] 48 25 [8] [] [8] [] 1 24 dir2 dir1 a2 a1 oe2 oe1 b2 b1 fct16245 74fct16245 5v part [8] [] [8] [] 48 25 [8] [] [8] [] 1 24 note: this is a rev 3 change it was to gpiob[0], but that was needed for the smart card detect 31 33 70 55 29 [] [2..25] [] [0..31] romconn data adr ce oe wr wp reset
systems research center palo alto, ca title: by: $date: 1997/05/16 00:47:47 $ mark hayter rcs $revision: 1.37 $ sequoia nc* nc* cwe nc* nc* nc* .irq[1] note inverted wrt others! isa.irq[8] isa .aen .bale .~dack[0..3] .~dack[5..7] .drq[0..3] .drq[5..7] .~iochk .iochrdy .~iocs16 .~ior .~iow .~master .~memcs16 .~memr .~memw .~refresh .sa[0] .sa[1] .~sbhe .sd .~smemr .~smemw .clk .tc .~zws p5000* .~memw .~memr ~romcs ~romcs isa.~master nc* version: rev 4 .adr[2..27] .adr[31] .~ads .~be .~blast .~brdy .dnc .~eads nc* rh nc* rh p5000* p5000* nc* rh p5000* nc* nc* .wnr .~rdy .mnio .hlda .~reset vl rh p5000* rh p5000* nc* .sd[8..15] ided7 [8..15] [0] [1] [2] [3] [4] [5] [6] [7] [0] [1] [2] [3] [4] [5] [6] rh rh rh rh rh rh rh gnd* isa.~ior isa.~ior .~iocs16 .irq[14] .iochrdy rh vl.~reset idedata ~idecs ~idecs[1] .sa[0] .sa[1] .sa[2] .bale .~iow .~ior note: this ide interface uses the isa command pins directly therefore if turbo mode is used (eide) other isa peripherals may get confused. this should be tested and the restriction of only standard ide modes may be imposed. .~reset nc* .~brdy .data .hlda .hold .~lgnt0 .~lreq0 .~local .~lrdy .~rdy saen nc* rh gnd* 6 of 16 p5000* sequoia.pc gnd* gnd* p5000* p5000* sequoia.gpiob rh p5000* sequoia.smart[0..3] gnd* ma[1] ma[2] ma[3] ma[4] ma[5] ma[6] ma[7] ma[8] ma[9] ma[10] ma[11] ma0a gnd* gnd* p5000* gnd* gnd* p5000* gnd* gnd* gnd* gnd* 160/176 package not dlc processor reserved bd delay other cpu type reserved bads,bdev delay misc config misc config [2..0] = rev 4 misc config reserved internal rtc see register 100h of sequoia-1 [2..5] [6..9] [10..13] [14..17] [2..5] [6..9] [10..13] [14..17] vl.adr .sa [0..18] .sd[0..7] [18] rh vl.adr[18] note: only loads on adr 18 are rom and umi0 sequoia.intr .sreset [1] gnd* u1: i1:10k i2:10k i3:10k i5:10k i6:100k i11:100k i12:100k i13:100k i14:100k i15:100k i16:100k i17:100k i18:100k i10:100k i7:100k i8:100k i9:100k i26:100k i27:100k i28:100k i30:100k i29:4k7 i34:4k7 clocks.clk32k i31:100k i32:100k i33:100k u2: i35:4k7 i36:100k sequoia.smart[4..7] i37:20k u4: i38:0r i39:33r i40:33r i41:33r i42:33r i43:33r i44:33r i45:33r i46:100k data adr we oe ce am29f040 22 24 31 [0..18] [] [0..7] [] u5: u6: u7: u8: i47:33r data ior iow balel hcs adr reset iocs16 irq iochrdy idecon 27 31 32 1 [0..2] [] [0..1] [] 28 23 25 [0..15] [] ideale ~idew ~ider ~hcs idea ~ideres sequoia.pwrgood sequoia.rcrst nc* clocks.clk14m clocks.clk33m i48:47r clocks.sequref clko1 rh i49:22r rh i50:33r rh i51:33r clocks.vlbus1 clocks.vlbus2 clko1 isa.reset rh cv twopin p5000* i52:33r i53:1k i54:0.01uf gnd* the 'beep' speaker gizmo plugs in here bootrom: pin out ok for rom/eprom/flash 128kx8, 256kx8, 512kx8 +5v flash may be programmed in system +12v flash may need adr[18] disconnected and the pin tied to p5000* (its vpp) sequoia.pbat t3904 p5000* i25:100k [0] [1] [0] [1] [2] [0] [1] ~idecs[0] .sd .irq[3..12] .irq[14..15] bd nc* nc* rhr ma ma0a ma0b ma0b rhr rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi cv gnd* bc1:1uf bc2:0.1uf note: bypass caps (0.1uf and 0.001uf each) for address buffer and bootrom from sheet 1 p5000* sequoia.nmi sequoia.nmi cvt3 sqbypass pwr 9x0.1uf, 5x1uf, 4x10uf for sequoia plus 3x0.1uf for ide buffers (sheet 13) tp [1] tp12: tp tp13: tp tp16: saen tp tp17: tp tp18: .~brdy tp tp19: .~rdy tp tp20: .wnr sp:tp s0 s1 s2 s5 s6 s7 s8 s9 sa sb sd se sf sg sh si sj sk sl sm sn sp bads bdev bser fs1xclk so ~idebufen sequoia.smi vcccore2 vcccore1 spndrst rstdrv rstcpu rcrst pwrgood cpuclko2 cpuclko1 clkin wbnwt wnr stpclk sreset smiact smi rdy nmi mnio lock ken hlda hitm flush eads dnc cache brdy blast be ads a20m a31 adr fs1xclk bser bdev bd bads romcs master kbrst kbcs irq8 acpwr vlb lb swtch pc gpiob gpio c32kin css3 tagwe tagd7 tagd0 sramce cwe ca3b ca3a mden ma ma0b ma0a dramwe sequoia1 pt86c768a2 93 121 120 [1..11] [] 92 127 128 [0..1] [] 174 144 136 135 125 57 [0..3] [] [0..1] [] [0..9] [] 47 122 123 124 70 68 66 54 69 81 [0..7] [] 82 83 80 [2..27] [] 172 162 155 [0..3] [] 160 153 152 158 161 35 150 163 40 149 159 173 156 37 33 32 38 157 151 59 167 165 55 56 34 65 67 39 148 cpuclk in14mhz gpio rstdrv deturbo rdy nmi lrdy local lreq0 lgnt0 intr ignne hold hlda hitm ferr d brdy bint fs1xclk bser bdev bd bads xddir spkr saen turbo idecs idebufen ided7 zws tc sysclk smemw smemr sd sbhe sa1 sa0 refresh memw memr memcs16 master irqh irq irq1 iow ior iocs16 iochrdy iochk drq2 drq dtack dack bale aen sequoia2 pt86c718a2 115 123 [0..3] [] [5..7] [] [0..3] [] [5..7] [] 117 118 124 51 50 94 [3..12] [] [14..15] [] 116 111 113 114 121 108 109 110 [0..15] [] 49 48 122 84 120 135 136 [0..1] [] 126 127 139 42 144 [0..7] [] 143 141 146 142 171 [0..31] [] 166 159 161 162 165 163 4 3 [0..2] [] 41 160 172 140 119 [4..7] [] 137 157 oe4 oe3 oe2 oe1 a4 a3 a2 a1 y4 y3 y2 y1 fct16244 74fct16244 5v part [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] [4] [] 1 48 25 24 g2 g1 a7 a6 a5 a4 a3 a2 a1 a0 y7 y6 y5 y4 y3 y2 y1 y0 hct244i 74hct244 18 16 14 12 9 7 5 3 2 4 6 8 11 13 15 17 1 19 cv bc3:0.1uf p5000* sequoia.umics 1 19 [] [8] [] [8] 74hct245 hct245 b a g dir 1 19 9 8 7 6 5 4 3 2 11 12 13 14 15 16 17 18 74hct245 hct245i b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 g dir rh p5000* i55:4k7 .~lrdy sequoia.~ferr sequoia.pc[4] gnd* the sequoia burst bus needs pullups on the control lines if the power-down feature is used the bd data lines also need pullups p5000* i24:10k p5000* i23:10k rhi rhi bads bdev sequoia.pc[0] s8
systems research center palo alto, ca title: by: $date: 1997/05/13 18:11:02 $ mark hayter rcs $revision: 1.30 $ version: rev 4 pci and umis 7 of 16 .~ads .mnio .wnr .dnc .~be .adr .data .~local[2] .~rdy .~lreq0 .~lgnt0 .~blast .~brdy .~loc0or1 rh p5000* nc* vl .~reset rh p5000* rh p5000* pci.~gnt[1] pci.~gnt[3] configiuration links select irq14,15 not req/gnt2 select blast not hiaddr .~frame .ad .~cbe .~irdy .~trdy .~stop .~devsel .par .~perr .~lock .~req[0] .~gnt[0] .~req[3] .~gnt[3] .~inta .~intb .~intc .~intd .~irdy .~trdy .~stop .~devsel .~perr .~serr .~lock .~req[3] .~inta .~intb .~intc .~intd .~frame .~req[0] .~req[1] p5000* isa sequoia.umics note: umics may be useful for upper address bit decoding note: idsel comes from ad[17]. don't care abput loading since there is only one umi slot. additional pci devices could use ad[18..31] but then loading might become an issue. note: only config type 0 cycles supported by via chip, so no bridges on the umi p5000* .~local[2] note: pullups for unpopulated bridge p5000* .~lreq0 vl.adr[19..25] note: address lines 19..25 are not used on internal isa nor by most networking chips, so they come unbuffered from the vl bus rh .drq[0] rh .drq[1] rh .drq[2] rh .drq[3] rh .drq[5] rh .drq[6] rh .drq[7] rh rh rh rh .~iochk .iochrdy .~iocs16 .~ior rh .~iow p5000* p5000* p5000* p5000* p5000* gnd* gnd* gnd* gnd* gnd* gnd* gnd* rh .irq[1] rh .irq[3] rh .irq[4] rh .irq[5] rh .irq[6] rh .irq[7] rh .irq[9] gnd* gnd* gnd* gnd* gnd* gnd* gnd* rh .irq[10] rh .irq[11] rh .irq[12] rh .irq[14] rh .irq[15] gnd* gnd* gnd* gnd* gnd* rh p5000* rh p5000* rh p5000* rh p5000* rh p5000* .~master .~memcs16 .~memr .~memw .~refresh p5000* rh .~zws [15] nc* [9..11] [5] isa.irq isa.~iochk i1:4k7 i2:4k7 i3:4k7 i4:10k i5:10k i6:10k i7:10k i8:10k i9:10k i10:10k i16:4k7 i15:1k i41:330r i11:10k i12:10k i43:330r i44:330r i13:10k i14:10k i40:330r i21:100k i22:100k i23:100k i24:100k i25:100k i26:100k i27:100k i28:100k i29:100k i30:100k i31:100k i32:100k i42:330r u1: i50:2k7 i51:2k7 i52:2k7 i53:2k7 i54:2k7 i55:2k7 i56:2k7 i57:2k7 i58:2k7 i59:2k7 i60:2k7 i61:2k7 i62:2k7 i63:2k7 i64:2k7 i17:4k7 i18:4k7 clocks.vlbus1 .~req[1] .~gnt[1] p5000* .sd[8..15] i37: p5000* .sd[0..7] in out r8x10k i36: r8x10ka out in .~inta .~intb .~intc .~intd .~frame .~irdy .~devsel .~lock .par .~trdy .~stop .~perr .~serr rh i67:2k7 p5000* rh i68:2k7 p5000* rh rh rh gnd* i69:4k7 i70:4k7 i71:4k7 note: only use of these adr bits .adr[28] .adr[29] .adr[30] rhr rhi rhi rhr rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi note: 3 pairs of bypass caps from sheet 5 p0 p1 p2 147 102 [] [9..11] 143 97 136 101 152 96 148 117 116 104 103 105 115 [] [0..31] [] [2..31] [] [0..3] 4 3 2 1 149 16 15 99 98 120 159 119 118 128 129 121 5 138 139 141 142 137 160 [] [0..3] [] [0..31] 46 151 vl -- pci vt82c505 pclk frame ad cbe irdy trdy stop devsel par perr serr lock req0 req1 gnt0 gnt1 req3 gnt3 inta intb intc intd cclk ads mio wr dc be ca cd ldevo lrdy rdyrtn ldevi lreqo lgnti blast brdy reset wback eads iochk irq5 irq irq14 irq15 .ad .~gnt[0] .~req[0] .~cbe vl.~reset .ad[17] pci .aen .bale .reset .~iochk .iochrdy .~iocs16 .~ior .~iow .tc .clk .~zws .~memr .~memw .~memcs16 .~refresh .~sbhe .~smemr .~smemw .sd .irq[10] .irq[11] .irq[12] .~dack[3] .~dack[5] .~dack[6] .drq[3] .drq[5] .drq[6] .sa i72:4k7 p5000* rhi 227 27 226 26 225 25 224 24 223 23 222 22 221 21 [] [0..3] 218 118 18 217 117 17 [] [0..31] umipci ad inta intb intc intd gnt req cbe clk frame irdy devsel lock sdone sbo par rst idsel trdy stop perr serr 118 126 124 122 [] [0..15] 220 20 219 119 19 218 18 217 117 17 216 16 215 115 15 214 114 14 213 113 13 212 112 12 211 [] [19..25] [] [0..18] umiisa sa sah upcs aen bale reset dacka dackb dackc drqa drqb drqc iochk iochrdy iocs16 ior iow tc clk zws memr memw memcs16 refresh sbhe smemr smemw sd irqa irqb irqc master .~master .~rdy note: lreq0 pullup for pclk=cclk rh p5000* pci.~gnt[0] i73:4k7 pclk synchronous clocks.vlbus1 clocks.vlbus1 this selection makes the umi slot be pci config device 6 nc* nc* these are two holes for standoffs to fix the umi cards. basically 0.153 hole with min .180 clearance mnt1: mnt2: hole153 hole153 vl.~boff
systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.28 $ .sa[0..15] .aen .sd[0..7] .~dack[0..3] .drq[0..3] .iochrdy .irq[1] .irq[3..12] .~ior .tc isa nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* .~iow .~zws rh ppack ppafd ppspr ppbusy pperr ppinit ppd pppe ppslct ppstb p5000* ppack ppafd ppspr ppbusy pperr ppinit ppd pppe ppslct ppstb .out .in .rts .ri .dtr .dsr .dcd .cts .out .in .rts .ri .dtr .dsr .dcd .cts ser2t cv i15:4k7 i16:4k7 gnd* i17:4k7 p5000* i18:4k7 ts p5000* gnd* p5000* ~md ~kd ~kc ~mc xp mkpwr i19:1000pf filter ptc ~mdata ~mclk ~kdata ~kclock ser1t superio version: rev 4 8 of 16 .id0 .rx1 .tx .id2 .id1 .id3 .irsl2 gpio2 gpio1 nc* nc* nc* nc* ser1t.out p5000* p5000* ser2t.rts ser2t.out ser2t.dtr p5000* ser1t.dtr ser1t.rts p5000* ir.irsl2 fdc,kbc,rtc inactive no x bus clock source 32.768khz pnp motherboard, config @015ch not nsc test note:internal 30k pulldown i1:10k i2:10k i3:10k i4:10k u1: nc* nc* nc* nc* nc* rh p5000* nc* rh p5000* rh gnd* clocks.clk32k nc* i5:10k i8:1k i9:10k i6: i7: i10:33r i11:33r i12:33r i14:33r i20:4k7 i21:4k7 i22:4k7 i23:4k7 i24:4k7 i25:4k7 i26: i27:4k7 i28:4k7 i29:4k7 i30:680pf i32:680pf i31:330pf i33: i34:330pf gnd* ir strobe select paper data init err busy selectpr afd ack pport parallel 10 14 17 11 15 16 [0..7] [] 12 13 1 ser1shdn .reset vbat nc* r8x4k7 8 8 c8x330 r8x33 8 i13: ppdx fb25 dbas16 dbas16 rhr rhr rhi rhi rhi rhi rhi rhi rhi rhi rhi rhi rvi rvi rvi rvi chi chi chi chi rhi rhi rhi rhi p5000* note: six of these go to sheet 9 note: national recommend six 0.1uf bypass caps iobypass pwr 12x0.1uf (sheet14) gpio1[0] gpio1[1] gpio1[2] gpio1[3] u2:93c46hostid p5000* i35:10k rhi s0 s1 s2 s3 s4 s5 s6 s7 s8 2 3 4 1 eeprom microwire serrom cs do di clk gpio1[4] gpio1[1] gpio1[2] gpio1[3] u3:93c86 2 3 4 1 eeprom microwire serrom cs do di clk note: hostid is pre-programmed with a digital uid for the network interface note: this 16kbit eeprom is nonvolatile storage for the firmware to keep settings, it is partitioned by digital, nci and firmworks u6 u5 u4 u3 u2 u1 l6 l5 l4 l3 l2 l1 dualmd6 dualmdin6 lower 1 2 3 4 5 6 upper 11 12 13 14 15 16 nc* gnd* nc* nc* nc* rv p5000* i36:10k i37:10k i38:10k gnd* i39: sequoia.pwrgood ~softres rvi rvi dbas16i x2c x1c x1 wdo vcch vbat switch ring por onctl gpio2 gpio1 cs2 cs1 cs0 wp wgate wdata trk0 step rdata index hdsel dskcng drate0 dir densel zws wr tc rd mr irq15 irq14 irq irq1 iochrdy drq dack data aen adr stb slct pe pd init err busy astrb afd_dsrtb ack sout1 sin1 rts1 ri1 dtr1 dsr1 dcd1 cts1 sout2 sin2 rts2 ri2 dtr2 dsr2 dcd2 cts2 gpio20 id3 irsl2 irsl1id1 irsl0id2 irtx irrx1 irrx2id0 p21 p20 p17 p16 p12 kbclk kbdat mclk mdat pc87307 105 104 103 102 106 107 108 109 110 79 80 81 158 78 77 70 157 141 142 143 144 145 146 147 148 131 132 133 134 135 136 137 138 113 119 118 111 116 117 [0..7] [] 115 114 112 [0..15] [] 30 [0..7] [] [0..3] [] [0..3] [] 32 36 [3..12] [] 48 49 51 33 35 34 31 94 90 84 99 92 97 95 91 96 89 93 98 68 71 72 [0..6] [] [3..7] [] 67 159 69 66 64 65 156 50 62 63 .irq[15] sequoia.~ferr
systems research center palo alto, ca title: by: $date: 1997/05/12 00:28:29 $ mark hayter rcs $revision: 1.29 $ serial i/o gnd* .dtr .rts .cts .dcd .ri .dsr nc* ser1t the ir from the superio supports irda and consumer ir only 38khz consumer ir is provided here tx frequency is set by software, but receiver module is tuned version: rev 4 9 of 16 p5000* gnd* ir .tx .rx1 p5000* gnd* .id0 .id1 .id2 .id3 id links for cir only, don't do plug'n'play stage 2 other rx module options are tmfs5nn0 for nn = 30, 33, 36, 37, 38, 40, 56 as the center frequency in khz led rh led rh sequoia.pc[5] sequoia.pc[6] sequoia.pc[7] sequoia.pc[8] sequoia.pc[9] sequoia.scl sequoia.gpiob[1] sequoia.sda note: these are not really sequoia signals but open collector versions at 3.3v they are used to make the i2c for sdram type detect gnd* p5000* gnd* gnd* nc* gnd* rh rh rh rh p5000* rh p5000* rh p5000* nc* nc* rh gnd* clocks.clk3m ser2t.out smin smin rh rh ser2t.in .out .in it is in the required 1mhz - 5mhz range en r5o r4o r3o r2o r1o shdn r5i r4i r3i r2i r1i t4i t3i t2i t1i t40 t3o t2o t1o c2m c2p c1m c1p vm vp max211 13 17 12 14 15 16 2 3 1 28 7 6 20 21 9 4 27 23 18 25 8 5 26 22 19 24 i1:'0.1uf' i2:'0.1uf' i3:'0.1uf' i4:'0.1uf' i5:'0.1uf' u1: u2: i6:'4k7' i7:'4k7' i8:'10k' i9:'0r' i10:'0r' u3: i11:'4k7' i12:'4k7' i13:'4k7' i14:'4k7' i15:'4k7' i16:'4k7' i17:'4k7' i18:'4k7' i27:'14r' p5000* i20:'330r' i21:4.7uf i19:'15k' u4: i23:'330r' i24:'330r' i25:'330r' i26:'330r' i29:'5mm,yellow' i30:'5mm,green' ird 3 elt1 mmf 2 4 1 t2n02 sequoia.smart[4] sequoia.smart[6..7] sequoia.smart[1] sequoia.smart[0] sequoia.smart[2] v1p v1m v2p v2m vp vm ser1r.dtr ser1r.rts ser1r.out ser1r.in ser1r.cts ser1r.dcd ser1r.ri ser1r.dsr ser1shdn gnd* gnd* smrst smclk smio virtx yl gl note: pc[5] and pc[6] can be programmed to flash leds sharp ir options are is1u60 rx module (38khz) and gl560 or gl561 irled. note that packages differ! note: use 3.579 mhz clock (cpu core clock) here tsip5201 rh i31:'470r' smvcc sequoia.smart[5] rh i32:'10k' gnd* smartcard interface uses sequoia gpio bits [0..7] smart[0..3] always inputs on reset, [4..7] may be parity 0 - high to power card 1 - high to reset card 2 - card data in 3 - card detect in (low if card) 4 - clock for card 5 - data for card 0 0 0 1 1 0 1 1 data, clock o/c 7 6 3.579mhz clock, gpio data gpio clock, gpio data 3.579mhz clock, uart t2907a cva4 6 9 1 8 2 3 7 4 5 9pin d rs232 gnd dtr rts txd rxd cts dcd ri dsr tsip5201 i22:'14r' note: nat semi ir front end reference suggests use of two ir leds. note: tssp4400 are similar with light output on side ir1: ir2: rhr rhr rhr rhr rhr rhi rhi rhi cv cv cv cv cv irdr irir act05 12 13 10 11 8 9 6 5 4 3 2 1 act05 12 13 10 11 8 9 6 5 4 3 2 1 l0 l1 l2 l3 p5000* 1 3 2 tfms5380 vg out vs gnd* p5000* c0 c1 c2 c3 c4 [] [2] 13 12 11 10 3 4 5 6 15 9 1 7 74f153 f153 ya ea yb eb i0a i1a i2a i3a i0b i1b i2b i3b sel alternatively put the ir leds in right angle mounts p5000* biled gnd* note: these two leds are only populated on debug or development boards rhi rhi hole125 hole125 nc* nc* these holes are for supports for the smartcard reader when a bare board is used sm0: sm1: rh sequoia.gpiob[0] ~cardins note: this is a rev 3 change gpiob[0] is wake0 and can trigger a fiq both on card insert and card removal i33:'470r' ledlnk gnd* note: either the link wire or board mounting led may be used onehole gnd* this hole sits between the ir leds to allow a cable to be used to bezel mounted leds in place of pcb mounted ones carddet2 carddet1 c8rsvd2 c7io c6vpp c5gnd c4rsvd1 c3clk c2rst c1vcc smrtpins iso7816 1 3 5 7 2 4 6 8 slot 9 10
systems research center palo alto, ca title: by: $date: 1997/05/17 00:51:49 $ mark hayter rcs $revision: 1.32 $ audio version: rev 4 .reset .~ior .~iow .sa[0..11] .aen .sd[0..7] .sd[8..15] nc* .drq[5] .~dack[5] .drq[0] .~dack[0] .drq[1] .~dack[1] .drq[3] .~dack[3] .irq[9] .irq[5] .irq[7] .irq[10] .irq[15] rh p5000* nc* nc* nc* nc* nc* nc* nc* gnd* nc* nc* nc* note: slight difference between 888 and 1887 for the dsp serial port. this arrangement should be fine for not using the port cv note: use xtal here if the clk14m is not accurate enough cv cv cv cv cv cv cv nc* rh gnd* gnd* cv rh rh cmr cv agnd avcc cv ch ch ch ch ch cv ch avcc nc* cv avcc agnd p5000* note: care with layout need single connection point for agnd to gnd note: output amp is directly (not cap) coupled since vref/cmr is used as the reference below this line is the analog power/ground domain 10 of 16 isa clocks.clk14m i1:1k i2: i3:10uf i4:0.1uf i5:0.1uf i6:7k5 i7:7k5 i8:10uf i9:47uf i10:0.1uf below this line is the analog power/ground domain gnda cmr mic fdxi fdxo auxr auxl liner linel vdda1 aoutl aoutr pcspko cinr foutr cinl foutl vref mute volup voldn pcspki amode dackbd drqd dackbc drqc dackbb drqb dackba drqa irqe irqd irqc irqb irqa xi xo datah datal aen adr iowb iorb reset gpo1 gpo0 mclk msd fmsel dx dr dclk fs frmstb fmcsb td tc tb ta swd swc swb swa mso msi es888 56 55 32 31 30 29 28 27 26 25 18 79 80 81 82 83 86 84 85 54 53 78 72 73 [0..11] [] 9 [0..7] [] [8..15] [] 76 77 71 70 69 68 67 65 66 63 64 61 62 59 60 22 52 19 20 21 44 33 42 34 43 50 49 48 41 46 47 37 38 36 35 39 45 40 i11:2k2 i12:2k2 i13: i14:2k2 i15:2k2 i16:2k2 i17:2k2 p5000* i18:150pf i19:0.01uf i20:0.01uf i21:0.01uf i22:0.01uf i23:2k2 i24:2k2 i25:2k2 i26:2k2 i27:1m i28:0.01uf i29:1m i30:0.01uf i31:1m i32:0.01uf i33:1m i34:0.01uf sa sb sc sd ta tb tc td mi mo moout miout pgame x1 y1 x2 y2 i35:4k7 i36:0.1uf i37:0.22uf i38:1000pf i39:0.22uf i40:1000pf i41:10uf i42:0.1uf i43:330uf i44:10k i45:8k6 i46:10k i47:8k6 i48:330uf i50:0.1uf cmr fr cir cil fl aor aol vref ramp lamp gnd* 7 6 5 4 8 3 2 1 vee vcc - + - + p1 m1 o1 m2 o2 p2 ssm2135 fb25 fb25 rhi rhi rhr miin mic amode fmsel aold aord cmr rhr avccm rhr rhi rhi rhi rhi cha8 cha8 cva6 cva4 cva4 cva4 ptc rvi rvi rvi rvi rvi rvi rvi rvi note: four 0.1uf bypass capacitors (as suggested by ess) shown on sheet 11 pg nc* nc* the frmsrb out from the 888 becomes fsr in on the 1887 the fs in on the 888 becomes fsx in on the 1887 for using the port on both chips these would have to be linked in the 1887 case and not in the 888 case. for never using leave unlinked and rely on the internal pulldowns 101 111 103 110 102 left jack 201 211 203 210 202 center jack 301 311 303 310 302 right jack jacks 3.5mm three over female d (2 row) 15 pin 4 5 13 11 6 3 14 10 7 2 9 8 1 12 15 gameport audiogm midii midio pwr1 pwr2 pwr3 sw1 sw2 sw3 sw4 x1 y1 x2 y2 gnd1 gnd2 rsig3 rsw3 lsig3 lsw3 com3 rsig2 rsw2 lsig2 lsw2 com2 rsig1 rsw1 lsig1 lsw1 com1 nc* nc* nc* nc* rl ll ch i51:0.22uf rl ch i52:0.22uf ll miin agnd nc* nc* mike input is on combo connector on right of this page line output headphone output stereo stereo mono mike input rhr ro lo agnd had 10uf here :'es888 or es1887' the audio is designed to use either the es888 or es1887 codec the main difference is that the 1887 includes fm synth, it is also more expensive (about $3 more) the 1887 is also slightly more configurable software for the 888 should work with the 1887 apart from a few lines of setup code (and the lack of synth) note: rev 4 change tie off unused inputs ch i53:0.22uf ch i54:0.22uf ch i55:0.22uf ch i56:0.22uf ch i57:0.22uf ch i58:0.22uf agnd i0 i1 i2 i3 i4 i5
systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ hal murray rcs $revision: 1.16 $ version: rev 4 11 of 16 ethernet r1:4k99 gnd* .~memr .~memw .~memcs16 .~refresh .~ior .~iow .~iocs16 .iochrdy .~sbhe .aen isa nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* .reset .sa .sd .irq[10] .irq[11] .irq[12] .irq[5] .drq[5] .drq[6] .drq[7] .~dack[5] .~dack[6] .~dack[7] xtal2 x1:20mhz rh rh cv r2:100r r3:24r3 r4:24r3 c1:68pf cv c3:0.1uf 8 7 6 9 11 1:1.4 3 2 1 14 16 1:1 for 10baset xfmrt rim rip rom roc rop tom top tim tic tip gnd* c5:1000pf, 1kv c4:1000pf, 1kv cv c2:0.1uf r5:680r r2, r3, and r4 are setup for 100 ohm twisted pair. other values are possible. see cs8900 data sheet, page 123. p5000* r6:680r rhr rhi lanled linkled x1 cs do di sk x2 1 2 3 6 for 10baset rj45 rm rp tm tp rm rp tm tp rdm rdc rdp tdm tdp tdc cvhv cvhv led led l1:5mm,green l2:5mm,yellow rh rh sequoia.pc[2] vl.adr[19] note: changed these caps from 10n to 1n p5000* four digital, three analog recomended by crystal one for serial eeprom, four for audio (sheet 10) iobypass pwr 12x0.1uf (sheet14) clk di do cs serrom microwire eeprom 1 4 3 2 u2:93c46 u1: tum tup res lgrn lyel the serial eeprom is not populated on the digital reference design it is shown here for reference only (for example a umi manufacturer may use it) 12 14 16 11 13 15 35 30 31 32 36 64 33 62 61 49 34 28 29 63 75 7 [] [0..15] 60 [] [0..18] 87 88 91 92 82 81 80 79 84 83 98 97 4 6 5 3 2 17 77 93 76 78 99 100 cs8900 lanled linkled bstatus test res sleep csout elcs eecs eedo eedi eesk x1 x2 dop dom dip dim cip cim rdm rdp tdm tdp addr a19 data chipsel reset aen memr memw memcs16 refresh ior iow iocs16 iochrdy sbhe irq0 irq1 irq2 irq3 dmarq0 dmarq1 dmarq2 dmack0 dmack1 dmack2
systems research center palo alto, ca title: by: $date: 1997/05/14 03:07:47 $ mark hayter rcs $revision: 1.28 $ version: rev 4 12 of 16 power gnd* rv cv p5000* rv pbat cv rh i1:'51k' i2:'1k' i3:'1k' i4:'20k' i5:'0.1uf' i6:'4700pf' i7:'br2032/keystone 1061' twopin i8:'10k' i9:'10uf' + bat t3904 rcrst t2907a cva4 p5000* p3300* gnd* gnd* i30:'22uf' i32:'22uf' i31:'22uf' i33:'121r' i34:'100r' va3 i35:'100r' gnd* rv cva5 cva5 cvt6 rv i36: p2000* cv cv cv cv c11:'0.1uf' c12:'0.1uf' c13:'0.1uf' c14:'0.1uf' cv cv cv cv cv cv c01:'1000pf' c02:'1000pf' c03:'1000pf' c04:'1000pf' c05:'1000pf' c06:'1000pf' gnd* gnd* p2000* cv c15:'0.1uf' cv c16:'0.1uf' p3300* p2000* gnd* gnd* i20:'22uf' i22:'22uf' i21:'22uf' i23:'121r' i24:'71r5' va2 gnd* rv cva5 cva5 cvt6 i26: p5000* vbat dbav70 hole125 nc* hole125 nc* hole125 nc* hole125 nc* hole125 nc* hole125 nc* hole125 gnd* hole125 gnd* hole125 nc* h0: h1: h2: h3: h4: h5: h8: h7: h6: note: battery is 3v li coin cell br2032 in a smt holder p12000 gnd* rh rvi rvi rvi rv i11:'10uf' i10:'22k' cva4 twopin pwrgood tp tp21: tp tp22: rp2:'tp' rp1:'tp' lt1086 vin adj vout lt1086 vin adj vout b0 b1 b2 r3 b3 p12 gnd2 gnd1 p5 idepwr 1 2 3 4 note: these are the mounting holes, with the two near the connectors grounded they have a .220 diameter pad with a .125 fhs plated hole plugp outer inner pwrjack 1 2 3 nc*
cv cv cv cv cv c11:'0.1uf' c12:'0.1uf' c13:'0.1uf' c14:'0.1uf' c15:'0.1uf' c21:'1uf' c22:'1uf' c23:'1uf' c24:'1uf' c25:'1uf' pwr pwr gnd* gnd* c31:'10uf' pwr gnd* cv cv cv cv c16:'0.1uf' c17:'0.1uf' c18:'0.1uf' c19:'0.1uf' c26:'1uf' cva4 c32:'10uf' cva4 c33:'10uf' cva4 c34:'10uf' cva4 note: sequoia1 gets 0.1uf + 1uf for each of the five power groups plus 1uf extra note: sequoia2 gets 0.1uf + 10uf for each of the four power groups note: three 0.1uf for the ide buffers cv cv cv c41:'0.1uf' c42:'0.1uf' c43:'0.1uf' pwr gnd* cvt3 cvt3 cvt3 cvt3 cvt3 cvt3 sequoia bypass 13 of 16 systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.8 $ version: rev 4
cv cv cv cv cv cv cv cv c11:'0.1uf' c12:'0.1uf' c13:'0.1uf' c14:'0.1uf' c15:'0.1uf' c16:'0.1uf' c17:'0.1uf' c18:'0.1uf' cv cv c19:'0.1uf' c20:'0.1uf' pwr gnd* c:'22uf' pwr gnd* cva5 cv cv c21:'0.1uf' c22:'0.1uf' pwr gnd* systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ mark hayter rcs $revision: 1.8 $ version: rev 4 i/o bypass 14 of 16
cv cv cv cv cv c11:'0.1uf' c12:'0.1uf' c13:'0.1uf' c14:'0.1uf' c15:'0.1uf' cv cv cv cv cv c01:'1000pf' c02:'1000pf' c03:'1000pf' c04:'1000pf' c05:'1000pf' pwr pwr gnd* gnd* c:'22uf' pwr gnd* cva5 systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ rcs $revision: 1.8 $ version: rev 4 bypass (5) 15 of 16 hal murray
cv cv cv cv cv cv cv cv c11:'0.1uf' c12:'0.1uf' c13:'0.1uf' c14:'0.1uf' c15:'0.1uf' c16:'0.1uf' c17:'0.1uf' c18:'0.1uf' cv cv cv cv cv cv cv cv c01:'1000pf' c02:'1000pf' c03:'1000pf' c04:'1000pf' c05:'1000pf' c06:'1000pf' c07:'1000pf' c08:'1000pf' cv cv c19:'0.1uf' c20:'0.1uf' cv cv c09:'1000pf' c10:'1000pf' pwr pwr gnd* c:'22uf' pwr gnd* cva5 systems research center palo alto, ca title: by: $date: 1997/04/30 09:20:59 $ rcs $revision: 1.10 $ version: rev 4 hal murray 16 of 16 bypass (10) gnd*

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